Arkle Res Regulatory News (ARK)

10 Sep 2007 07:45

ARC International (LSE:ARK) and Cadence Design Systems, Inc.(NASDAQ:CDNS), today announced a new automated Common Power Format(CPF)-enabled low-power reference design methodology (LP-RDM) has beenimplemented in ARChitect, ARC's patented processor configuration tool.This LP-RDM together with the Cadence(R) Low Power Solution ensuresthat ARC's new Energy PRO technology is captured in RTL andimplemented consistently throughout the design flow to GDSII. Users ofthe reference design flow may achieve up to a four-fold reduction ofIP core power. See companion ARC press release dated September 10,2007 for more details on Energy PRO. £ "ARC and Cadence have been jointly developing a reference designflow based on the SI2 industry standard Common Power Format," saidMichael Horne, group director, Industry Alliances at Cadence. "The newdesign flow represents the culmination of this effort. Using theCadence Low Power Solution enabled by CPF, ARC has successfullyemployed a standard 90nm low-power standard cell library to performnetlist synthesis, verification, floorplanning, and routing of an ARCcore to a TSMC 90nm target process. The result was a right-first-timetest design that achieved its target power specifications." £ "ARC and Cadence have worked together to make great strides inachieving the lowest power in SoC designs using ARC's configurablecores and subsystems at joint customers," said Paul Holt, vicepresident, product development and services at ARC International. "Theresult of our experiments with the new flow shows that customers usingARC's Energy PRO technology and employing the new LP-RDM based onCadence technology will achieve power savings of up to four fold overconventional low-power flows of the past." £ Energy PRO in the Encounter Low-Power Flow £ The ability to custom configure a processor core or subsystemusing ARChitect is a fundamental advantage provided to SoC designersof ARC-based(TM) chips. ARC's future products based on Energy PROtechnology will extend this advantage by incorporating specificpower-management features in the product. ARC will provide developmenttools which will recognize the power intent of the product and ensurethat the hardware design achieves its optimal energy efficiency. £ Cadence Low-Power Solution scripts are integrated into ARC'sconfiguration tool in a Reference Design Flow (RDF) library. ARChitectallows the designer to implement various Energy PRO features whiletaking advantage of Virage Logic's Area, Speed and Power (ASAP)Logic(TM) standard cell libraries and Ultra-Low-Power standard cellarchitecture. ARChitect then produces RTL containing the Energy PROdesign intent for input to the Cadence Encounter(R) digital IC designplatform - a key component of the Cadence Low-Power Solution. Usingthe industry standard SI2 Common Power Format, the Encounter platformprovides RTL to netlist synthesis, verification, floor planning androuting for a TSMC 90nm process technology. Thus SoC designers caneasily configure an Energy PRO processor and be assured that all itslow-power capability automatically propagates through the entireEncounter flow to final layout. £ Availability £ The new low-power reference design methodology (LP-RDM)implemented in ARChitect is available now. For more information,contact ARC sales representatives or e-mail info@arc.com. £ About Cadence Design Systems, Inc. £ Cadence enables global electronic-design innovation and plays anessential role in the creation of today's integrated circuits andelectronics. Customers use Cadence(R) software and hardware,methodologies, and services to design and verify advancedsemiconductors, consumer electronics, networking andtelecommunications equipment, and computer systems. Cadence reported2006 revenues of approximately $1.5 billion, and has approximately5,200 employees. The company is headquartered in San Jose, Calif.,with sales offices, design centers, and research facilities around theworld to serve the global electronics industry. More information aboutthe company, its products, and services is available atwww.cadence.com. £ About ARC International plc £ ARC International is the world leader in configurable mediasubsystems and CPU/DSP processors. Used by over 140 companiesworldwide, ARC's configurable solutions enable the creation of highlydifferentiated system-on-chips (SoCs) that ship in hundreds ofmillions of devices annually. ARC's patented subsystems and cores aresmaller, consume less power, and are less expensive to manufacturethan competing products. £ ARC International maintains a worldwide presence with corporateand research and development offices in Silicon Valley and St. Albans,UK. For more information visit www.ARC.com. ARC International islisted on the London Stock Exchange as ARC International plc(LSE:ARK). £ Cadence and Encounter are registered trademarks, and, the Cadencelogo is a trademark of Cadence Design Systems, Inc. All othertrademarks are the property of their respective owners. £ ARC and the ARC logo are trademarks or registered trademarks ofARC International. All other brands or product names contained hereinare the property of their respective owners. This press release maycontain certain "forward-looking statements" that involve risks anduncertainties, including the development, implementation, and releaseof features described herein. These are at the sole discretion of ARCInternational. Licenses from 3rd parties for certain software andessential patents may be required depending on licensee'suse/implementation. For other factors that could cause actual resultsto differ, visit the company's Website as well as the listingparticulars filed with the United Kingdom Listing Authority and theRegistrar of Companies in England and Wales. Copyright Business Wire 2007